1. Field of the Invention
This invention relates to the testing of electronic equipment, and more specifically, to the testing of interconnections between integrated circuits in a computer system.
2. Description of the Related Art
As dependence on various electronic systems continues to increase, so too does the need for reliability. From a hardware perspective, reliability may be ascertained by testing at various levels. These levels of testing include system tests, printed circuit assembly (i.e. circuit board) tests and integrated circuit tests. Such tests may ensure proper fabrication and assembly of the various components of the system. However, these tests may have limitations.
One such limitation involves testing the interconnections (signal lines) of a printed circuit assembly for an electronic system (such as a computer system) at the operational speed which the system is configured to run. Operational speed may be defined as the clock frequency of a computer system bus. Such interconnections may be tested by various methods including in-circuit test (ICT) or boundary scan. Typically, these types of testing methods are limited to a maximum frequency that is significantly less than the clock frequency of the assembly to be tested. Testing by such methods may allow an assembly with faulty interconnections to pass at maximum tester frequency. These same assemblies may fail when tested at the intended operational clock frequency, or worse, when in an operational environment. Faulty interconnections may be caused by various defects such as cold or insufficient solder joints, damaged signal lines, and damaged connector pins.
Further compounding the problems outlined above is the difficulty in isolating a faulty interconnection that passes a low frequency test, but fails at operational speed. In many situations, such failures may require time-consuming visual inspections and/or the use of other troubleshooting techniques. The time consumed in isolating the fault may add significant cost to a printed circuit assembly. Furthermore, if a particular fault is not diagnosed correctly unnecessary rework and component replacements may occur, further adding to the cost of the assembly.
A partial solution to some of the above problems is to incorporate built-in self test (BIST) into the design of a computer system. With BIST functionality designed into a system, some testing of interconnections may be accomplished. However, the BIST functionality employed in many systems may be limited. For example, many typical BIST systems are xe2x80x9cpoint-to-pointxe2x80x9d, testing signal links strictly from one chip to another at a given time. Such a system using BIST may not be configured to tests multiple links from a single chip simultaneously. Some BIST systems may also test for interconnects at low speeds, which may not be effective in detecting a signal line that is defective when operating at full speed. Furthermore, many BIST systems require a centralized system controller which is used to coordinate tests and configurations for the various chips in the system. Using such a system controller may require the use of valuable printed circuit board space which could otherwise be used to implement other functions.
The problems outlined above may be in large part solved by a system and method for testing signal interconnections using built-in self test (BIST). In one embodiment, BIST functionality is designed into the various chips of a computer system, which are mounted upon printed circuit boards. Instead of using a single BIST system controller, each chip of the system includes its own central logic unit, which may be used to configure its own various ports for BIST, as well as performing test pattern generation. Chips may also include transmit links and receive links for transmitting and receiving test patterns. In general, a given chip of the system may act as either a master or a slave chip during testing. All chips within the system are configured to allow testing to occur at the operational clock frequency of the computer system. Performing the test at the operational clock frequency may allow the test to ensure good signal integrity on the interconnections between chips. Interconnections tested may include those that pass through connectors as tests may be conducted between two or more chips on different circuit boards within the computer system.
In general, the system and method for testing interconnections using BIST may be implemented in a variety of systems, and is not limited to computers. Such systems may include digital signal processing equipment, telephones and telecommunications equipment, wireless communications equipment, or consumer electronic devices.
Several different methods are contemplated for invoking the BIST. In one embodiment, the BIST is invoked upon the insertion of a hot-pluggable printed circuit board into an operating computer system and may ensure good signal integrity between the various chips of the printed circuit board. The BIST may also ensure good signal integrity between components on the hot-pluggable circuit board and other components of the computer system on other printed circuit boards. Once the BIST successfully completes, communications between the various chips mounted upon the printed circuit board and the computer system may begin. In another embodiment, the BIST may be invoked by a signal from automated test equipment (ATE), such as an in-circuit tester. During manufacturing test, the tester may send a signal to a printed circuit assembly with BIST features. Upon completion of testing, the printed circuit board may return a signal to the tester indicating that testing is complete, along with the results. Other embodiments wherein the BIST is invoked by a power-on reset or initial power-up of a computer system are possible and contemplated as well.
Another embodiment of the BIST system includes the ability to test multiple interconnections from a single master chip. In some embodiments, a single master chip may transmit test patterns simultaneously to a plurality of slave chips sharing a common bus. Prior to the transmission of the test patterns, the master chip may program a sequence at which the slave chips will respond to receiving the test. After receiving the transmitted test pattern from the master chip, each slave chip may then respond by returning a corresponding test pattern to the master chip, in the sequence designated by the master chip. This may prevent bus conflicts when testing interconnections between multiple chips across a common bus.
In other scenarios, a single master chip may transmit test patterns to a plurality of slave chips that do not share a common bus. Test patterns for each slave chip are transmitted through different signal blocks of the master chip with corresponding test patterns received from the slave chips through the same ports. The corresponding test patterns received from each of the slave chips may then be checked by a receive unit within the master chip in order to verify the tested interconnection.
Yet another feature of the BIST system is the ability to characterize operating margins and input/output (I/O) performance. For example, during testing the BIST system may lower logic voltage levels and measure setup time, or raise logic voltage levels and measure hold time. This may allow the determination of worst and best case conditions for signal transfers between chips, and may be especially useful in predicting when certain chips are likely to fail.
Thus, in various embodiments, the system and method for testing interconnections using built in self-test may advantageously allow testing of signal interconnections at operational clock speed. The use of a central logic unit within each master chip may eliminate the need for a single BIST system controller. Implementing transmit and receive links may allow a given chip to act as either a master chip or a slave chip. The ability of the system to allow multiple tests to be conducted simultaneously may allow for shorter test times. Similarly, the ability of the system to allow tests to be conducted between any two properly configured chips of the system may allow the testing of interconnections between two or more chips on different circuit boards.